sFPDP (VITA 17.1) Release 7.1 now available! This release adds support for Xilinx Versal ACAP and Intel Agilex FPGA device families. This release introduces unique entity names to allow for easier integration into designs with other StreamDSP IP cores, and also corrects a problem in UltraScale and UltraScale+ example GT's where the "Keep Idle" feature was enabled which will cause problems linking with single-idle encoded streams.
Contact us at firstname.lastname@example.org or visit us at www.streamdsp.com for more information.
Release 7.1 supports the following FPGA families...
Altera / Intel
Zynq UltraScale+ MPSoc/RFSoC
If you are a current sFPDP (VITA 17.1) customer with an active maintenance agreement and wish to receive this new update, please let me know.